How are High-Speed FPGA-Based Circuit Board Designed

It would be nice if high-speed PCB design could be as simple as connecting schematic nodes and as elegant as it looks on a computer monitor. However, unless designers are new to PCB design, or are extremely lucky, actual PCB design is usually not as easy as the circuit design they are engaged in. PCB designers face many new challenges until the design finally works and someone confirms the performance. This is exactly the current state of high-speed PCB design – design rules and design guidelines are constantly evolving and, with luck, they lead to a successful solution.

The vast majority of PCBs are schematic designers who are proficient in the working principles and interactions of PCB components and the various data transmission standards that make up the input and output of the board and may or may not know a little. What happens after conversion to printed circuit copper wires is the result of a collaboration between professional layout designers. Often, it is the schematic designer who is responsible for the success or failure of the final board. However, the more a schematic designer knows about good layout techniques, the better the chances of avoiding major problems.

If the design includes a high-density FPGA, there are likely to be many challenges that lie ahead of a well-designed schematic. Including hundreds of input and output port counts, operating frequencies in excess of 500MHz (possibly higher in some designs), and solder ball spacing as small as half a millimeter, all of these will lead to undesired interference between design units. mutual influence.

The first challenge is likely to be the so-called concurrent switching noise (SSN) or concurrent switching output (SSO). A large amount of high-frequency data flow will cause problems such as ringing and crosstalk on the data lines, and ground bounce and power supply noise problems on the power and ground planes will affect the performance of the entire board.

To address ringing and crosstalk on high-speed data lines, switching to differential signaling is a good first step. Since one line on the differential pair is the sink (Sink) end and the other provides the source current, the effect of induction can be eliminated fundamentally. When transmitting data using a differential pair, since the current remains localized, it helps reduce "bounce" noise from induced currents in the return path. For radio frequencies up to hundreds of MHz or even several GHz, signal theory shows that the maximum signal power can be delivered when the impedance is matched. When the transmission line is not well matched, reflections will occur, and only a part of the signal is transmitted from the sending end to the receiving device, while the other part will bounce back and forth between the sending end and the receiving end. How well the differential signal is implemented on the PCB will play a big role in impedance matching (among other things).

The differential trace design is based on the impedance-controlled PCB principle. Its model is somewhat like coaxial cable. On an impedance-controlled PCB, the metal plane layer can be used as a shield, the insulator is an FR4 laminate, and the conductors are the signal trace pairs (see Figure 1). The average dielectric constant of FR4 is between 4.2 and 4.5. Due to unknown manufacturing errors, it is possible to cause over-etching of the copper lines, resulting in impedance errors. The most accurate way to calculate PCB trace impedance is to use a field analysis program (usually 2D, sometimes 3D), which requires a direct solution of Maxwell's equations for the entire PCB batch using finite elements. The software can analyze EMI effects in terms of trace spacing, trace width, trace thickness, and insulation layer height.

The 100Ω characteristic impedance has become the industry standard value for differential cables. A 100Ω differential line can be made with two 50Ω single-ended lines of equal length. Since the two traces are close to each other, the field coupling between the traces will reduce the differential mode impedance of the traces. To maintain the 100Ω impedance, the width of the trace has to be reduced a bit. As a result, the common-mode impedance of each wire in a 100Ω differential pair will be slightly higher than 50Ω.

In theory the size of the trace and the material used determine the impedance, but vias, connectors and even device pads will introduce impedance discontinuities in the signal path. It's usually impossible to do without these things. Sometimes, for more reasonable layout and routing, it is necessary to increase the number of PCB layers, or add functions such as buried holes. Buried holes only connect some layers of the PCB, but while solving the transmission line problem, it also increases the manufacturing cost of the board. But sometimes there is no choice at all. As signal speeds get faster and space gets smaller, additional requirements like buried vias start to increase and should become a cost factor for PCB solutions.

With stripline routing, the signals are sandwiched by FR-4 material. In microstrip, one conductor is exposed in the air. Because air has the lowest dielectric constant (Er= 1), the top layer is most suitable for laying out some critical signals, such as clock signals or high-frequency SERial-DESerial (SERDES) signals. The microstrip routing should be coupled to the underlying ground plane, which reduces electromagnetic interference (EMI) by absorbing some of the electromagnetic field lines. In stripline, all electromagnetic field lines couple to the reference plane above and below, which greatly reduces EMI. Broadside-coupled stripline designs should be avoided if possible. This structure is susceptible to differential noise coupled in the reference plane. In addition, a balanced manufacturing of the PCB is required, which is difficult to control. In general, it is relatively easy to control the line spacing on the same layer.

Another important aspect to determine whether the actual performance of the PCB is as expected needs to be controlled by adding decoupling and bypass capacitors. Adding decoupling capacitors helps reduce the inductance between the PCB's power and ground planes and helps control the impedance of signals and ICs everywhere on the PCB. Bypass capacitors help provide a clean power supply (provide a charge bank) to the FPGA. The traditional rule is that decoupling capacitors should be placed wherever PCB routing is convenient, and the number of FPGA power pins determines the number of decoupling capacitors. However, the ultra-high switching speed of FPGA completely breaks this stereotype.

In a typical FPGA board design, the capacitors closest to the power supply provide frequency compensation for current variations in the load. To provide low frequency filtering and prevent supply voltage drops, large decoupling capacitors are used. The voltage drop is due to a lag in the regulator's response when the circuit is designed to start up. This large capacitor is usually an electrolytic capacitor with better low-frequency response, and its frequency response ranges from DC to several hundred kHz.

Each FPGA output change requires charging and discharging the signal lines, which takes energy. The function of the bypass capacitor is to provide local energy storage over a wide frequency range. In addition, small capacitors with low series inductance are required to provide high-speed current for high-frequency transients. The slow-response large capacitor continues to provide current after the energy of the high-frequency capacitor is consumed.

The large number of current transients on the power bus adds to the complexity of FPGA design. Such current transients are often associated with SSO/SSN. Inserting very low inductance capacitors will provide localized high frequency energy that can be used to cancel switching current noise on the power bus. This decoupling capacitor, which prevents high-frequency current from entering the device power supply, must be very close to the FPGA (less than 1 cm). Sometimes many small capacitors are connected in parallel for local energy storage of the device and to respond quickly to changing current demands.

In general, the routing of decoupling capacitors should be absolutely short, including the vertical distance in the vias. Even a small increase will increase the inductance of the wire, which will reduce the effectiveness of decoupling. As signal speeds increase, it becomes increasingly difficult to easily move data across a circuit board. Several other techniques can be utilized to further improve the performance of the PCB.

The first and most obvious approach is simple device layout. It is common sense to design the shortest and most direct paths for the most critical connections, but don't underestimate this. Why bother to adjust the signal on the board when the simplest strategy can get the best results?

An almost equally simple approach is to consider the width of the signal lines. When the data rate is as high as 622MHz or even higher, the skin effect of signal conduction becomes more prominent. When the distance is long, very thin traces on the PCB (such as 4 or 5 mil) will cause a large attenuation to the signal, just like a low-pass filter with no attenuation designed, its attenuation varies with increases with increasing frequency. The longer the backplane and the higher the frequency, the wider the width of the signal lines should be. For backplane traces longer than 20 inches, the line width should be 10 or 12 mils.

Usually, the most critical signal on the board is the clock signal. When a clock line is too long or poorly designed, it can amplify jitter and skew downstream, especially as speed increases. You should avoid using multiple layers to carry the clock, and not have vias on the clock lines, as vias will increase impedance variation and reflections. If the inner layer must be used to route the clock, then the upper and lower layers should use the ground plane to reduce delay. When designing with an FPGA PLL, noise on the power plane can add to the PLL jitter. If this is critical, it is possible to create a "power island" for the PLL that utilizes a thicker etch in the metal plane to isolate the PLL's analog and digital supplies.

For signals exceeding 2Gbps, more costly solutions must be considered. At such high frequencies, the backplane thickness and via design have a large impact on signal integrity. Backplane thicknesses of up to 0.200 inches work well. When there are high-speed signals on the PCB, the number of layers should be as few as possible, which can limit the number of vias. In thick boards, the vias connecting the signal layers are longer and will form a transmission line branch on the signal path. Buried vias can be used to solve this problem, but the manufacturing cost is high. Another option is to use a low loss dielectric material such as Rogers 4350, GETEK or ARLON. These materials can nearly double the cost compared to FR4 materials, but sometimes this is the only option.

Finally, and one of the best ways, is to refer to a reference board provided by the FPGA manufacturer. Most manufacturers provide source layout information for reference boards, although special requests may be required due to proprietary information issues. These boards often contain standard high-speed I/O interfaces because FPGA manufacturers need them when characterizing and qualifying their devices. Keep in mind, however, that these boards are often designed for multiple purposes and may not be an exact match for specific design needs. Even so, they can serve as a starting point for creating solutions.

Of course, this article only touched on some basic concepts. Any one of the topics covered here could be discussed in an entire book. The key is to figure out what the goal is before investing a lot of time and effort into PCB layout design. Once the layout is complete, redesigning even a slight adjustment to the trace width can be time-consuming and costly. PCB layout engineers cannot be relied on to make designs that meet actual needs. It is up to the schematic designer to provide guidance at all times, make smart choices, and take responsibility for the success of the solution.