Choosing The Right Test Technology For PCB Interconnects

PCB interconnection design technology includes testing, simulation and various related standards, among which testing is a method and means to verify various simulation analysis results. Excellent testing methods and means are necessary conditions to ensure interconnection design analysis. For traditional signal waveform testing, the main focus should be on the length of the probe lead to avoid unnecessary noise introduced by Pigtail. This paper mainly discusses new applications and developments of interconnect test technology.

In recent years, with the continuous improvement of the signal rate, the test object has undergone significant changes. It is no longer limited to the traditional use of an oscilloscope to test signal waveforms. Power ground noise, synchronous switching noise (SSN), and jitter (Jitter) have gradually become The focus of interconnection design engineers, some instruments in the RF field have been applied to interconnection design. Test instruments commonly used in interconnect design, including spectrum analyzers, network analyzers, oscilloscopes, and the various probes and fixtures used by these instruments, have undergone significant changes in the way these test instruments are used to accommodate increasing signal rates. This article takes these test instruments as tools, and mainly introduces the development of interconnection design and test technology in recent years from the following aspects.

1. The calibration method of the test

2. Modeling method of passive components

3. Power integrity test

4. Test method of clock signal jitter

At the end of the article, it will also briefly introduce the development of future testing technology in conjunction with the just-concluded DesignCon2005 conference. Among the three commonly used test instruments, the calibration method of the network analyzer is the most rigorous, followed by the spectrum analyzer, and the calibration method of the oscilloscope is the simplest. Therefore, we mainly discuss the calibration method of the network analyzer here. There are three commonly used calibration methods for network analyzers, Thru, TRL, and SOLT.

The essence of Thru is normalization. During calibration, the network analyzer records the test result (S21_C) of the fixture. In the actual test, directly divide the test result (S21_M) by S21_C to obtain the test result of the DUT (S21_A) . Thru calibration ignores reflections caused by mismatches in the test fixture and electromagnetic coupling in space, so it has the lowest calibration accuracy. This calibration method can be used when only S21 is tested and the test accuracy is not high.

In non-Coaxial structures such as PCB, it is sometimes necessary to test the characteristics of traces, vias, connectors, etc. In this case, the test instrument supplier does not provide standard calibration parts, and it is difficult for testers to make good open circuit, short circuit, matching load and other calibration parts at the test calibration port. Therefore, traditional SOLT calibration cannot be done. The advantage of using TRL calibration is that no standard calibration parts are required, and the test calibration port can be extended to the required position. At present, TRL calibration has been widely used in PCB structure testing.

SOLT is generally considered as a standard calibration method. There are 12 calibration error parameters in the calibration model, and various errors are calibrated by using short circuit, open circuit, load and through. Since test instrument suppliers usually only provide Coaxial calibration parts, the SOLT calibration method cannot be used in non-Coaxial structures.

The above three calibration methods can be analyzed in detail by using the signal flow graph, and each error parameter has a corresponding parameter in the signal flow graph. Through the signal flow diagram, the error sensitivity of various calibration methods can be clearly understood, so as to understand the error range of the actual test. A point that needs to be made here is that even the standard SOLT calibration method ignores five error parameters in the calibration model. Typically, these five error parameters do not affect calibration accuracy. However, if you do not pay attention to the design of the calibration jig during use, the phenomenon of inaccuracy will occur.

A standard source is provided inside the spectrum analyzer for calibration. When calibrating, you only need to connect the internal standard source to the input port through the test fixture. The time required for calibration is about 10 minutes. The calibration of the oscilloscope is simpler, just connect the probe to the internal standard source and confirm. The time required for calibration is about 1 minute.

As the signal rate continues to increase, the role of passive devices in the signal chain is becoming more and more important. The accuracy of system performance simulation analysis often depends on the model accuracy of passive devices. As a result, testing and modeling of passive components has gradually become an important part of the interconnect design of various equipment suppliers. Commonly used passive components are as follows:

1. Connector

2. PCB routing and vias

3. Capacitance

4. Inductance (magnetic beads)

In high-speed signal integrity designs, connectors have the greatest impact on the signal chain. For frequently used high-speed connectors, the usual practice is to make a calibration fixture according to the TRL calibration method, and test and model the connector for simulation analysis. The test modeling method of PCB traces and vias is similar to that of connectors. TRL calibration is also used to move the test port to the required position, and then test modeling.

Capacitance models are used in signal integrity analysis, and more importantly, in power integrity analysis. The capacitance modeling instruments commonly used in the industry are impedance analyzers and network analyzers, which are respectively suitable for different frequency bands. Impedance analyzers are suitable for low frequency bands, and network analyzers are suitable for high frequency bands. If a network analyzer is used for power integrity testing in the specific actual test, it is recommended to use a network analyzer in the entire frequency band of capacitance modeling to ensure the consistency of modeling and application. Due to the small impedance of capacitors, they are usually connected in parallel when modeling with a network analyzer. At present, the unsolved problem in the capacitance modeling in the industry is how to eliminate the mutual coupling between the fixture and the capacitor, so as to reduce the influence of the fixture on the modeling results.

In traditional power supply design, inductors (magnetic beads) are often used to isolate the power supply to reduce noise interference. In actual design, it often occurs that the isolation inductance (magnetic bead) is removed, and the ground noise of the power supply is reduced instead. This is due to the resonance of the inductor (bead) with other filter components. To avoid this from happening, it is necessary to model and simulate the inductor (bead) to avoid resonance. The commonly used inductance (magnetic bead) modeling method in the industry also uses a network analyzer. The specific method is similar to the capacitance modeling method. The difference is that the inductance (magnetic bead) is modeled in series and the capacitance is modeled in parallel.

The modeling of the above passive devices is mainly used in signal integrity and power integrity. In recent years, the simulation analysis of EMI is gradually developing, and the test modeling of EMI passive devices has gradually become the focus of interconnection design. . Figure 1 shows the impedance curve of the capacitor.

As the power of the chip continues to increase and the operating voltage continues to decrease, the noise of the power supply has gradually become the object of attention in the interconnection design. From the perspective of the test object, the power integrity test can be divided into two steps, the power system characteristic test and the power ground noise test. The former is a test of the performance of the power supply part of the system (passive test), and the latter is a direct test of the power ground noise when the system is working (active test). Synchronous switching noise can also be classified as power ground noise.

When testing the performance of the power system, a network analyzer is usually used, and the test objects are Self-Impedance and Transfer-Impedance of the power system. Under normal circumstances, the impedance of the power system is much smaller than the system impedance of the network analyzer (50 ohms), so it is only necessary to do a straight-through calibration during the test, and the impedance of the power system can be obtained by using the formula S21=Z/25.

You can use a spectrum analyzer and an oscilloscope to test the ground noise of the power supply. The input port of the spectrum analyzer cannot be connected to a DC component. Therefore, when testing the ground noise of the power supply, DC-Blocking must be connected in series in the test fixture. The input impedance of the spectrum analyzer is 50 ohms, and the impedance of the power ground network is generally milliohm level, so the test fixture will not affect the system under test. The input impedance of the oscilloscope changes with different settings. Taking Tektronix's TDS784 as an example, its low-frequency cut-off frequency changes with the coupling method and system impedance.

The method described above is to test the power ground noise on the board, but what really affects the operation of the chip is the power ground noise inside the chip. At this time, it is necessary to use the synchronous switching noise test to determine the power ground noise inside the chip. Assume that the chip has N IO ports, keep one of them static, and the other N-1 are flipped at the same time, and test the signal waveform on the static network, that is, the synchronous switching noise. Synchronous switching noise includes both power ground noise and crosstalk between different signals in the package. Currently, there is no way to completely distinguish the two.

In some high-end products, jitter has gradually become an important indicator affecting product performance. Here we only briefly introduce how to use a spectrum analyzer to test clock signal jitter and locate problems. The jitter test of data signals is not involved for the time being.

In most systems, the clock is generated by a crystal oscillator or a phase-locked loop. The jitter test of the clock signal is relatively simple, and does not require high-end test equipment, and the common spectrum analyzer can be used to locate the problem. The spectrum of an ideal clock signal is a clean discrete spectrum with components only at multiples of the clock frequency. If the clock signal jitters, side lobes will appear near these multipliers, and the jitter size is proportional to the power of these side lobes.

The specific method of using the spectrum analyzer to test the clock jitter is to randomly find a testable point on the clock signal link, connect the signal at this point to the spectrum analyzer through DC-Blocking, and observe the test results. Since the test fixture is a linear system, there is no need to worry about creating new spectral components. As mentioned above, the clocks are all generated by crystal oscillators or phase-locked loops. In this case, the main reason for introducing clock jitter is the power supply noise of crystal oscillators or phase-locked loops. Using the method introduced above to test the power supply noise of the crystal oscillator or phase-locked loop, and comparing it with the side lobe in the clock spectrum, the cause of the clock jitter can be basically determined. The solution to the problem is to redesign the filter circuit of the crystal oscillator or phase-locked loop according to the side lobes of the clock spectrum. In general, these problems can be solved by choosing a filter capacitor reasonably.

DesignCon is the first conference in the field of interconnect technology every year. At the annual conference, in this year's DesignCon2005, there are mainly the following technological development trends:

1. The simulation and test of pure power integrity have been widely used in the industry, and it is no longer a difficult point in the analysis work.

2. The modeling of capacitance and inductance (magnetic beads) has been promoted in the industry, and its method has been relatively perfect.

3. The focus of interconnection design has shifted to packaging, and board-level analysis has become relatively mature, and the simulation and testing of synchronous switching noise has gradually become an issue of concern to the industry.

4. Jitter test methods and standards have gradually become a concern of the industry. Many test equipment suppliers launched their own jitter analyzers at the conference.

This paper briefly introduces the test objects and test methods in the field of interconnection design. With the continuous improvement of the signal rate, some new test contents gradually appear, including power ground noise, passive device modeling, jitter and so on. Based on his own work experience, the author proposes a test method for these new test contents. In the traditional signal waveform test, the main consideration should be to reduce the length of the ground wire to avoid the Pigtail coupling into the noise and reduce the test accuracy. In the future interconnection design, due to the increase of signal operating frequency, the focus of work will shift to chip packaging, and related testing and modeling technologies will become the focus of work.