Printed Circuit Board Design Output and Via Cost

PCB printed circuit board design output and parasitic capacitance of vias, parasitic inductance of vias and vias in high-speed PCB, related issues of drilling design costs.

1.  Design output

The PCB board design can be output to a printer or output as a light drawing file.  The printer can print the PCB board in layers, which is convenient for designers and reviewers to check;  the light drawing file is handed over to the board manufacturer to produce the printed board.  The output of light drawing files is very important, which is related to the success or failure of this design.  The following will focus on the precautions for outputting light drawing files.

a. The layers that need to be output are wiring layer (including top layer, bottom layer, middle wiring layer), power layer (including VCC layer and GND layer), silk screen layer (including top layer silk screen, bottom layer silk screen), solder mask layer (including top layer solder mask) and bottom solder mask), and additionally generate a drill file (NC Drill).

b. If the power layer is set to Split/Mixed, then select Routing in the Document item of the Add document window, and use Pour Manager's Plane Connect to copper-clad the PCB diagram before each output of the light drawing file;  if it is set to CAM Plane, select Plane, when setting the Layer item, add Layer25, and select Pads and Viasc in the Layer.25 layer.  In the Device Setup window (press Device Setup), change the value of Aperture to l99.

c. When setting the Layer of each layer, select the Board outline.

d. When setting the Layer of the silk screen layer, do not select Part Type, but select the top layer (bottom layer) and Outline, Text, and Line of the silk screen layer.

e. When setting the Layer of the solder mask layer, select the via hole to indicate that there is no solder mask on the via hole, and not to select the via hole to indicate the home solder mask, depending on the specific situation.

f. When generating the drilling file, use the default settings of PowerPCB without making any changes.

g. After all the light-painting files are output, open and print with CAM350, and check by the designer and reviewer according to the "PCB checklist"

Via is one of the important components of multi-layer PCB, and the cost of drilling usually accounts for 30% to 40% of the cost of PCB manufacturing.  Simply put, every hole on a PCB can be called a via.  From the perspective of function, vias can be divided into two categories: one is used for electrical connection between layers;  the other is used for device fixation or positioning.  In terms of process, these vias are generally divided into three categories, namely blind vias, buried vias and through vias.  Blind holes are located on the top and bottom surfaces of the printed circuit board, with a certain depth, for the connection of the surface circuit and the underlying inner circuit, and the depth of the hole usually does not exceed a certain ratio (diameter).  Buried vias refer to connection holes located in the inner layer of the printed circuit board, which do not extend to the surface of the circuit board.  The above two types of holes are located in the inner layer of the circuit board, and are completed by the through hole forming process before lamination.  During the formation of the via hole, several inner layers may be overlapped.  The third type is called through-hole, which penetrates the entire circuit board and can be used for internal interconnection or as a mounting location hole for components.  Because the through hole is easier to realize in the process and the cost is lower, most of the printed circuit boards use it instead of the other two kinds of through holes.  The via holes mentioned below are considered as through holes unless otherwise specified.

From a design point of view, a via is mainly composed of two parts: one is the drill hole in the middle, and the other is the pad area around the drill hole.  The size of these two parts determines the size of the via. .  Obviously, when designing high-speed and high-density PCBs, designers always want the vias to be as small as possible, so that more wiring space can be left on the board.  In addition, the smaller the vias, the greater their own parasitic capacitance.  Small, more suitable for high-speed circuits.  However, the reduction of hole size also brings an increase in cost, and the size of vias cannot be reduced indefinitely.  It is limited by process technologies such as drilling and electroplating: the smaller the hole, the more time it takes to drill.  The longer the hole is, the easier it is to deviate from the center position;  and when the depth of the hole exceeds 6 times the diameter of the hole, it cannot be guaranteed that the hole wall can be uniformly plated with copper.  For example, the thickness of a normal 6-layer PCB board (through hole depth) is about 50Mil, so the minimum drilling diameter that the PCB manufacturer can provide can only reach 8Mil.

2. Parasitic capacitance of vias

The via itself has parasitic capacitance to the ground. If it is known that the diameter of the isolation hole of the via on the ground layer is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric of the board substrate is often ε, the parasitic capacitance of the via is approximately: C=1.41εTD1/(D2-D1)

The main effect of the parasitic capacitance of the via on the circuit is to prolong the rise time of the signal and reduce the speed of the circuit. For example, for a PCB board with a thickness of 50Mil, if the inner diameter is 10Mil, the diameter of the pad is 20Mil. The distance between the pad and the ground copper area is 30Mil, then we can calculate the parasitic capacitance of the via through the approximate value of the above formula: C=1.41x4.4x0.05x0.02/(0.032-0.020)= 0.517pF, the rise time change caused by this part of the capacitor is: T10-90=2.2C(Z0/2)=2.2x0.517x(55/2)=31.28ps. From these values, it can be seen that although the effect of the rise and delay caused by the parasitic capacitance of a single via is not very obvious, if the via is used multiple times in the trace to switch between layers, the designer should still consider carefully.

3. Parasitic inductance of vias

Similarly, parasitic capacitance and parasitic inductance also exist in vias. In the design of high-speed digital circuits, the harm caused by parasitic inductance of vias is often greater than the influence of parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor and reduce the filtering effect of the entire power system. We can easily calculate the approximate parasitic inductance of a via with the following formula:

L=5.08h[1n(4h/d)+1] where L refers to the inductance of the via, h is the length of the via, and d is the diameter of the center hole. It can be seen from the formula that the diameter of the via hole has little effect on the inductance, while the length of the via hole has the greatest influence on the inductance. Still using the above example, the inductance of the via can be calculated as:

L-5.08x0.050[1n(4x0.050/0.010)+1]=1.015nH. If the rise time of the signal is 1ns, then its equivalent impedance is: XL=πL/T10-90=3.19Ω. Such impedance can no longer be ignored when high-frequency current passes through. It should be noted that the bypass capacitor needs to pass through two vias when connecting the power supply layer and the ground layer, so that the parasitic inductance of the vias will be multiplied.

4. Via design in high-speed PCB

Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the adverse effects caused by the parasitic effects of vias, you can try to do as much as possible in the design:

a. Considering both cost and signal quality, select a via size of a reasonable size. For example, for 6-10-layer memory module PCB design, it is better to use 10/20Mil (drilling/pad) vias. For some high-density small-sized boards, you can also try to use 8/18Mil vias. hole. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, consider using larger sizes to reduce impedance.

b. From the two formulas discussed above, it can be concluded that using a thinner PCB board is beneficial to reduce the two parasitic parameters of the via.

c. Try not to change the layers of the signal traces on the PCB, that is to say, try not to use unnecessary vias.

d. The pins of power supply and ground should be drilled with vias nearby. The shorter the leads between the vias and pins, the better, because they will lead to an increase in inductance. At the same time, the leads of power and ground should be as thick as possible to reduce impedance.

e. Place some grounded vias near the vias where the signal changes layers to provide the closest return path for the signal. It is even possible to place a few more ground vias on the PCB in large numbers. Of course, flexibility is also required in the design. The via model discussed earlier is the case where each layer has pads, and sometimes, we can reduce or even remove the pads of some layers. Especially in the case of a very high density of vias, it may lead to the formation of a circuit breaker on the copper layer. To solve this problem, in addition to moving the position of the via, we can also consider placing the via on the copper layer. The pad size is reduced.