PCB Board Design and Manufacture is a Basic Guide

Let's get started with some basic PCB design and manufacturing guidelines needed to ensure a successful design.

Get the layer stack first You'll be surprised how easy it is to jump right into your new design and start placing components around the board. For simpler boards that do not require impedance control, specific bus capacitors, or dense digital wiring, you can start laying out only on even-layer boards with standard layer thicknesses. Depending on the design, manufactured PCBS may not be able to create the functionality you expect.

PCB manufacturers can send you a laminated table to help ensure that your design is manufacturable For most designs, even microcontroller boards used for hobby purposes, you need to at least understand the arrangement of layers and material properties. Before you begin designing digital bus wiring or any impedance control wiring, send a copy of the standard layer stack to the manufacturing plant by email. If you don't, the manufacturer may produce your board using layer stacks that don't create the functionality you expect. Another risk is that you create layer stacks that cannot be manufactured, often because there is no material in stock that meets your lamination specifications.

Match copper weight to current density and laminate

When you choose a material or get an approved stack, don't be surprised if the manufacturer overrules your copper weight. You need to use the copper weight available on the manufacturer's material set, not just specify whatever copper weight you want. If you take the time to estimate the copper weight and track width required for a specific current density, such as on a power rail, you should make sure to specify the required weight when determining the lamination with the manufacturer.

Enforce copper to copper clearance

When you start a new PCB layout, the ECAD software will apply a set of default clearance rules that are conservative values for almost all PCBS. These values are often too conservative, so they are often ignored before starting a layout rather than being programmed with the correct gap values. Even worse, you may enter values that are too small, which will make you place elements too close together to make a board.

Note the polygonal copper paving placed near this track: the DRC engine has flagged a gap error along the track length in this window. The going-to-polygon gap rule should be set to ensure that these elements are not too close together, otherwise an unexpected short circuit between these elements may occur during the manufacturing process. The solution: Get the manufacturer's limits before you start placing them and program these values into your PCB project as design rules. If you want to make sure you're not hitting the most common gap violations, focus on the following gaps: wire to wire, wire/pad to polygon copper-laying, wire to pad, pad to pad.

The last two points will apply to SMD pads and landing pads for through-holes (through holes or component leads). Note that these values will be larger for heavier copper due to the need for etching compensation.

Overlapping hole

If you follow the previous clearance guidelines and set minimum pad spacing values, then you may have solved the design for manufacturing guidelines. If the holes are too close together, they may overlap each other due to offsets in the CNC holes. Each borehole hit is slightly off its ideal hit position, which needs to be taken into account when placing through and through hole leads. Similar problems can occur between drilling results across the plane, such as heat release and GND plane clearance as shown in the figure below. The two green areas show the gap between the pore walls and the planes of these networks; The remaining fragments here are very small and cannot be manufactured. The specific example shown below is an instance where such a manufacturing failure would not render a device inoperable, but this may not often be the case. If such defects occur on the surface layer between the two through-holes, there is a risk of bridging during the welding process, as the narrow copper features may be etched away during manufacturing.

The tight spacing between these two through-holes leaves very tiny pieces of copper on the flat layer, which will be overly etched and will not appear on the manufacturing board. The natural solution here is to use only larger pads, which is exactly what is needed to meet the basic IPC grade requirements; Use a minimum pad size (bit diameter) + 8 mil to ensure that the hole-to-hole clearance limit is almost always met.

Small feature size

When you start packing components and wiring onto a single board, it's easy to start making the wiring, drilling, and pads too small. Clearance rules already limit how far you can package all components, but an equally important design requirement is the minimum feature size. The two most common points you need to address are the maximum hole size and the width of the track. This is as simple as finding manufacturer feature sizes and programming them into your design rules. Typical manufacturing limits for most boards are 4 mil wire widths and 6 mil hole widths. For many simple boards that do not require impedance control, it is best to use a track width of 8 to 10 mil and a drilling diameter of 10 mil.

Solder shield fragment

This is an often overlooked aspect of the assembly process, designed to ensure that the solder stop opening reliably acts as a barrier against the flow of molten solder between two nearby components. Even if the pads are properly spaced, large choke openings on the NSMD pads can leave very thin choke channels between the pads.

The residual solder shield fragments between Q9 and Q10 will not be able to be manufactured because it is too thin. However, pad to pad clearance is still satisfactory. The solution here is to reduce the solder stop layer openings on these pads to 0 mil. You may also need to increase the spacing between these components by a few mils. The typical minimum solder shield fragment requirement here is 5 mil. When the solder stop layer fragment falls below the manufacturer's limit, it may break off after curing and form a channel where the two pads can be bridged with solder. The solution here is to apply additional spacing, or to reduce the solder stop layer openings on the affected pad so that a sufficiently large fragment is retained.

Overlapping screen printing layers

After the layout and wiring is complete, check the screen printing layer to ensure that there are no overlapping reference labels. If there are, you can move them around in the PCB layout until everything is clear. While this is not technically necessary for successful manufacturing or assembly, responsible manufacturers will still flag it as a problem during design reviews. A more important problem is the overlap of the screen printing layer with the pad/hole to which the solder is to be applied. Make sure to use the 3D model viewer or view Gerber directly to check this out. The list of guidelines above should address the most common DFM issues that can affect almost any design. When you implement the above guidelines in a project, it becomes part of the normal design process. Once these points have been codified into your design rules, as part of the design review, you can review the board at any time before putting it into production.