Noise Problems Caused By Layout of PCB Switching Power Supply

In circuit board design, the noise problem is a big problem that every designer will encounter. To fix noise problems, it typically takes hours of lab testing to find the real culprit. However, many times we find that the noise problem is caused by the improper layout of the switching power supply. How to solve such problems?

For the example switching regulator layout using the ADP1850 dual synchronous switching controller, the first step is to determine the current path for the regulator. Then, physical planning and power device considerations take place. Also, we need to understand that the current path determines where the device will be placed in this low-noise place-and-route design.

In a switching converter design, the high current path and the low current path are very close to each other. Alternating current (AC) paths carry spikes and noise, high direct current (DC) paths can generate considerable voltage drops, and low current paths tend to be sensitive to noise. The key to proper PCB layout is identifying the critical paths, then arranging the components, and providing enough copper area so that high currents don't disrupt low currents. Signs of poor performance are ground bounce and noise injected into the IC and the rest of the system.

A synchronous buck regulator design that includes a switching controller and the following external power components: high-side switch, low-side switch, inductor, input capacitor, output capacitor, and bypass capacitor. The arrows in Figure 1 indicate the direction of high switching current flow. Care must be taken to place these power components to avoid unwanted parasitic capacitance and inductance that can cause excessive noise, overshoot, ringing, and ground bounce.

Switch current paths such as DH, DL, BST, and SW need to be routed away from the controller to avoid excessive parasitic inductance. These lines carry high δI/δt AC switching pulse currents that can reach more than 3 A and last for several nanoseconds. The high current loop must be small to minimize output ringing and to avoid picking up additional noise. Low-value, low-amplitude signal paths, such as compensation and feedback components, are sensitive to noise. These paths should be kept away from switching nodes and power devices to avoid injecting unwanted noise.

PCB physical planning (floor plan) is very important. It is necessary to minimize the area of the current loop and arrange the power components reasonably so that the current flows smoothly and avoids sharp corners and narrow paths. This will help reduce parasitic capacitance and inductance, thereby eliminating ground bounce.

PCB Layout of a Dual Output Buck Converter Using the ADP1850 Switching Controller. Note that the layout of the power components minimizes the current loop area and parasitic inductance. Dashed lines indicate high current paths. Both synchronous and asynchronous controllers can use this physical planning technique. In asynchronous controller designs, Schottky diodes replace low-side switches.

Under heavy load conditions, the equivalent series resistance (ESR) of power MOSFETs, inductors, and bulk capacitors can generate a lot of heat. For effective heat dissipation, a large area of copper is placed under these power devices.

The heat dissipation effect of multi-layer PCB is better than that of 2-layer PCB. For improved heat dissipation and electrical conductivity, 2 oz thick copper should be used over the standard 1 oz copper layer. Vias connecting multiple PGND layers together can also help. A 4-layer PCB design has PGND layers on the top, third, and fourth layers.

This multiple ground plane approach isolates noise-sensitive signals. The negative terminals of the compensation device, soft-start capacitor, bias input bypass capacitor, and output feedback divider resistor are all connected to the AGND plane. Do not connect any high current or high δI/δt paths directly to the isolated AGND plane. AGND is a quiet ground plane where no large currents flow.

The negative terminals of all power supply components (such as low-side switches, bypass capacitors, input and output capacitors, etc.) are connected to the PGND plane, which carries high currents. The voltage drop within the GND plane can be so large that it affects output accuracy. Connecting the AGND plane to the negative terminal of the output capacitor with a wide trace can significantly improve output accuracy and load regulation.

The AGND plane extends all the way to the output capacitor, and the AGND and PGND planes connect to vias at the negative end of the output capacitor. Another technique for connecting the AGND and PGND planes, the AGND plane is connected to the PGND plane through a via near the negative terminal of the output bulk capacitor. A cross-section at a certain position on the PCB, the AGND layer and the PGND layer are connected through a via near the negative terminal of the output large capacitor.

To avoid degraded accuracy caused by interfering noise, the current-sense path layout of a current-mode switching regulator must be properly laid out. Dual-channel applications in particular pay more attention to eliminating any crosstalk between channels.

The ADP1850 dual buck controller uses the low-side MOSFET's on-resistance, RDS(ON), as part of the control-loop architecture. This architecture senses the current flowing through the low-side MOSFET between the SWx and PGNDx pins. Ground current noise in one channel can couple into adjacent channels. Therefore, it is important to keep the SWx and PGNDx traces as short as possible and place them close to the MOSFETs for accurate current sensing. Connections to the SWx and PGNDx nodes must use Kelvin detection techniques. Note that the corresponding PGNDx trace connects to the source of the low-side MOSFET. Do not connect the PGND plane to the PGNDx pins arbitrarily.

In contrast, for a dual-channel voltage-mode controller such as the ADP1829, the PGND1 and PGND2 pins are connected directly to the PGND plane through vias.

The feedback (FB) and current-limit (ILIM) pins are low-signal-level inputs, so they are sensitive to capacitive and inductive noise interference. FB and ILIM traces should be kept away from high δI/δt traces. Be careful not to loop the traces, causing unwanted inductance to increase. Adding a small MLCC decoupling capacitor (such as 22 pF) between the ILIM and PGND pins can help further filter the noise.

In a switching regulator circuit, the switching (SW) node is the noisiest place because it carries large AC and DC voltages/currents. This SW node requires a large area of copper to minimize the resistive voltage drop. Placing the MOSFET and inductor close to each other on the copper plane minimizes series resistance and inductance.

Applications more sensitive to EMI, switch node noise, and ringing can use a small snubber. The buffer is composed of a resistor and a capacitor in series, placed between the SW node and the PGND layer, it can reduce the ringing oscillation and electromagnetic interference on the SW node. Note that adding a snubber may slightly decrease overall efficiency by 0.2% to 0.4%.

The gate drive traces (DH and DL) also deal with high δI/δt, which tends to produce ringing and overshoot. These traces should be as short as possible. It is best to route directly, avoiding the use of feedthroughs. If vias must be used, use two vias per trace to reduce peak current density and parasitic inductance.

A small series resistor (approximately 2 Ω to 4 Ω) on the DH or DL pin slows down the gate drive, which also reduces gate noise and overshoot. Alternatively, a resistor can also be connected between the BST and SW pins. Preserving space with a 0 Ω gate resistor during layout increases flexibility for later evaluation. The increased gate resistance prolongs the gate charge rise and fall times, resulting in higher switching power losses in the MOSFET.

Understanding current paths, their sensitivities, and proper component placement is key to eliminating noise problems in PCB layout design. All Analog Devices power device evaluation boards use the above layout guidelines for optimum performance. Evaluation board documents UG-204 and UG-205 detail the layout of the ADP1850. Note that all switching power supplies have the same components and similar current path sensitivities. Therefore, the guidelines illustrated for the ADP1850 for a current-mode buck regulator also apply to the layout of a voltage-mode and/or boost switching regulator.