1. In a system where digital and analog coexist, I have seen two processing methods. One is to separate the digital ground from the analog ground. The leather or FB beads are connected, but the power supply is not separated; the other is that the analog power supply and digital power supply are connected separately with FB, and the ground is unified. Are these two methods the same?
Answer: It should be said that the principle is the same. Because power and ground are equivalent to high-frequency signals. The purpose of distinguishing between analog and digital parts is for anti-interference, mainly the interference of digital circuits to analog circuits. However, segmentation may result in an incomplete signal return path, affecting the signal quality of the digital signal and affecting the EMC quality of the system. Therefore, no matter which plane is divided, it depends on whether the signal return path is enlarged and how much the return signal interferes with the normal working signal. Now there are also some mixed designs, regardless of power supply and ground, when laying out, separate the layout and wiring according to the digital part and the analog part to avoid cross-regional signals.
2. In my PCB design, the CMOS driving signals of multiple analog multiplexers and analog switches located in the layout area of the multi-channel 12_bitCCD analog video signal sampling circuit must span the digital-analog division under multiple ADCs, (in different positions use Several 0 ohm resistors are shorted to the digital analog ground) The signal termination method at this time: the foreign model adopts the source terminal 120R, and the load terminal uses a 5K resistor to terminate 2 or 4 TTL compatible COMS loads to the ground. These traces are 6mil wide and about 4inch long, and the distance between the adjacent copper layers is about 5-8mil. Is this different from the 120 ohm source matching impedance, and whether the existence of the 5K resistor will increase the drive current and increase the interference of the digital part to the analog part. If the distance between multiple receivers is long such as 0.8inch, the 5K resistor How to adjust the position, or need to change the matching method. If the above matching method is correct, then how to calculate and how to treat the cross-split wiring that violates the design rules.
Answer: For cross-split signals, it is better to use a 0-ohm resistor to short-circuit the digital and analog grounds than to clamp the signal with parallel ground wires or use bypass capacitors. It is rare to use a 120-ohm series resistance at the source end. Is this driving signal a voltage-driven digital signal? Is there a power requirement to do this kind of termination? If it is really a voltage-effective digital signal, simulation model simulation is required to estimate the matching position and size.
3. In modern high-speed PCB design, in order to ensure the integrity of the signal, it is often necessary to terminate the input or output of the device. What are the methods of termination? What factors determine the way of termination? What are the rules? I hope that experts can give detailed answers to this or tell where to find the information to solve these problems.
Answer: Termination (terminal), also known as matching. Generally, according to the matching position, it is divided into active end matching and terminal matching. Among them, the source matching is generally resistor series matching, and the terminal matching is generally parallel matching. There are many ways, including resistor pull-up, resistor pull-down, Thevenin matching, AC matching, and Schottky diode matching. The matching method is generally determined by the BUFFER characteristics, topology conditions, level types and judgment methods, and the signal duty cycle and system power consumption should also be considered. The most critical issue in digital circuits is the timing problem. The purpose of adding matching is to improve the signal quality and obtain a determinable signal at the judgment moment. For level effective signals, the signal quality is stable under the premise of ensuring the establishment and holding time; for delayed effective signals, under the premise of ensuring the signal delay monotonicity, the signal change delay speed meets the requirements. There is some information about matching in the Mentor ICX product textbook. In addition, "High Speed Digital design a hand book of blackmagic" has a chapter dedicated to the terminal, which describes the role of matching on signal integrity from the principle of electromagnetic waves. I believe that after reading, the understanding of matching will be more thorough.
4. In today's wireless communication equipment, the radio frequency part often adopts a miniaturized outdoor unit structure, so the volume structure is greatly restricted. Therefore, the radio frequency part of the outdoor unit, the intermediate frequency part, and even the low frequency circuit part that monitors the outdoor unit are often It is deployed on the same PCB. What are the requirements for the material of such a PCB? How to prevent the interference between radio frequency, intermediate frequency and even low frequency circuits? Does the mentor have a solution in this regard?
Answer: Hybrid circuit design is a big problem. It is difficult to have a perfect solution. Generally, the radio frequency circuit is laid out and wired as an independent single board in the system, and there is even a special shielding cavity. Moreover, the RF circuit is generally single-sided or double-sided, and the circuit is relatively simple, all of which are to reduce the impact on the distribution parameters of the RF circuit and improve the consistency of the RF system. Compared with the general FR4 material, RF circuit boards tend to use high-Q substrates. This material has a relatively small dielectric constant, small transmission line distributed capacitance, high impedance, and small signal transmission delay. In hybrid circuit design, although RF and digital circuits are built on the same PCB, they are generally divided into RF circuit area and digital circuit area, which are laid out and wired separately. Use ground vias and shielding boxes between them. Mentor's board-level system design software, in addition to basic circuit design functions, also has a dedicated RF design module. In the RF schematic design module, a parameterized device model is provided, and a bidirectional interface with RF circuit analysis and simulation tools such as EESOFT is provided; in the RF LAYOUT module, a pattern editing function specially used for RF circuit layout and wiring is provided, and there are also The two-way interface of RF circuit analysis and simulation tools such as EESOFT can back-mark the results of analysis and simulation back to the schematic diagram and PCB. At the same time, using the design management function of Mentor software, design reuse, design derivation, and collaborative design can be easily realized. Greatly speed up the hybrid circuit design process. The mobile phone board is a typical mixed circuit design, and many large mobile phone design manufacturers use Mentor plus Angelon's eesoft as the design platform.
5. How to better avoid the possible impact of high-frequency parts on the system? For example, 206M CPU, 100M SDRAM, etc., how to deal with the layout and wiring to ensure the stability of the signal above 50M?
Answer: The key to high-speed digital signal wiring is to reduce the impact of transmission lines on signal quality. Therefore, the layout of high-speed signals above 100M requires that the signal traces be as short as possible. In digital circuits, high-speed signals are defined by signal rise delay time. Moreover, different types of signals (such as TTL, GTL, LVTTL) have different methods to ensure signal quality.
6. I have a question to ask. On a 12-layer PCB board, there are three power supply layers 2.2v, 3.3v, and 5v. It is no problem to put the three power supplies on each layer. How to deal with the ground wire is the same as the power supply. For one-to-one correspondence, one layer is still used, and the other two ground layers are only used as structural layers.
Answer: Generally speaking, the three power supplies are installed on the third floor, which is better for signal quality. Because it is unlikely that the signal will be split across plane layers. Cross-segmentation is a critical factor affecting signal quality that is generally ignored by simulation software. For power planes and ground planes, it is equivalent for high-frequency signals. In practice, in addition to considering signal quality, power plane coupling (using adjacent ground planes to reduce power plane AC impedance) and stacking symmetry are all factors that need to be considered.
7. For the PCB with all digital signals, there is an 80MHz clock source on the board. In addition to using wire mesh (grounding), in order to ensure sufficient driving capability, what kind of circuit should be used for protection. In addition, if a separate clock signal board is used, what kind of interface is generally used to ensure that the transmission of the clock signal is less affected.
Answer: 1. What is wire mesh (grounding)? Is it grid copper? 2. To ensure the driving ability of the clock, it should not be realized through protection. Generally, the clock is used to drive the chip. The general concern about clock drive capability is caused by multiple clock loads. A clock driver chip is used to convert one clock signal into several, and a point-to-point connection is adopted. When choosing a driver chip, in addition to ensuring that it basically matches the load and that the signal edge meets the requirements (generally, the clock is an edge-effective signal), when calculating the system timing, the delay of the clock in the driver chip must be taken into account. 3. The shorter the clock signal, the smaller the transmission line effect. Using a separate clock signal board will increase the signal routing length. And the ground power supply of the board is also a problem. For long-distance transmission, it is recommended to use differential signals. LVDS signals can meet the driving capability requirements, but your clock is not too fast, it is not necessary.
8. The same chip has a 2.8V digital power input and a 2.8V analog power input. Can the two be connected through an inductor and share an LDO. Just like digital ground and analog ground are connected together. Another: What is the 0 ohm resistor used for? Can it be interchanged with an inductor?
Answer: In general, LDO can be shared, the classic one is pi filter (not directly connected with inductor); but if the chip itself has high isolation requirements for digital and analog power supply, so that PI filter cannot meet the requirements, then separately Powered by different LDOs. The 0ohm resistor is generally used for redundant or optional design, similar to the role of a jumper, if the parasitic is not considered, there is no inductance, and it cannot function as a filter, so it cannot be interchanged with the inductance.
9. I would like to know the industry's design verification process of analog-digital mixed signals. As far as I understand, design verification plays a pivotal role in the design process and will directly affect the final success or failure of the chip. Design verification is divided into different levels, such as system-level verification, circuit block-level verification, analog-digital hybrid simulation and finally physical verification or post-simulation. How can design verification engineers ensure consistency between system verification and final layout-level verification? The reason for this question is that the time cost of simulation at different abstraction levels is different. It can be said that the gap is huge. The system-level abstraction level is relatively high, and the system simulation can be completed in a short period of time, but when it comes to layout Level verification, there is almost no way to do post-simulation of the entire chip. And if the post-simulation of the entire chip is not done, the consistency between the system simulation and the final chip implementation cannot be effectively guaranteed. I don't know what the more popular practice in the industry is. What I want to know is a general flow that breaks away from using tools.
Answer: This is a very good question, very professional. As you said, the time cost of simulation at different abstraction levels is different, and it is normal to have a time difference of one or even several orders of magnitude. Because as the amount of data increases, the amount of calculation for verification increases exponentially. Then when it comes to post-chip simulation, especially for the whole chip, the data volume of parasitic RC parameters will increase much more than the original number of devices and nodes, and the amount of calculation at this time will be astonishingly large. Support, it is very common for a verification to run for several months or even longer. At this time, in order to solve this problem, the usual practice is as follows: 1. Replace the spice-level simulator with a fast-spice-level simulator, that is, sacrifice a little precision in exchange for greater capacity and speed; 2. Let Digital The module becomes a real Digital. In the early digital-analog hybrid overall verification, due to the limitations of the verification tools, the gate-level of the digital circuit was often regarded as the transistor-level to run. The advantage of this is that the process is simple and the tool is single. But the disadvantages are also obvious. The amount of calculation is increased, and more calculation is placed in the part of the digital circuit that is not very needed. (Because digital-analog hybrid circuits often have more digital parts than analog parts) Even if the accuracy of some digital circuit parts can be lowered, it is a great waste of resources. The current trend is that when extracting the layout, the digital part is still commissioned at the gate-level, and a real digital-analog mixed-signal simulator is used for simulation. 3. Abstract the simulation part into a high-level AMS. This greatly improves the verification efficiency. In fact, many IPs also use AMS for overall verification.
10. I want to use an analog circuit to solve a 4th order differential equation for real-time control, which is faster. Specifically, the signal to be integrated calculated by the MCU is introduced into the analog integrator through the D/A, and the result of the integration is sent back to the MCU through the A/D for control. I don’t know if this is feasible, but the accuracy and interference are mainly considered. Can you recommend an integrating chip if possible, or should I build my own integrating circuit? Is it feasible to design the whole system including the adder and the multiplier as an analog chip? What should I pay attention to?
Answer: It seems possible. Maybe you can try the scheme first with MATLAB. Since I don't know the specifics, I can't recommend a specific approach to you. You can search the Internet to see if there is an integral chip that meets your specific requirements. If so, use a ready-made one. It is too troublesome to build the circuit yourself, and the performance cannot be guaranteed. Generally speaking, it is considered that the adder and multiplier are implemented with digital circuits, and it is common to integrate them together to make a hybrid chip. As a reminder, these tasks are unlikely to be done by one person alone. If you want to verify the feasibility of the system, you can consider running the simulation with AMS first.
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