Doing special things with circuit patterns is the hallmark of analog design. The sum of all important signals on the board equals one net. The net is a terrestrial net. At least one pin of each active component is grounded. RF equipment can use any of a variety of voltages and may require a dedicated power supply for each voltage required. The characteristic impedance depends on one or two ground planes.
As we pursued faster digital circuits, they also started behaving like analog circuits. Typical routing rules include fanning out surface mount pins with short segments and routing on inner layers as the main process. A particularly elegant layout can have the busses of associated traces run entirely on the outer layers.
In this case, we don't have to sandwich traces between ground planes to kill electromagnetic emissions (EMI). The savings is that we don't use vias to transition the signal to the inner layers. Printed circuit board design is always a balancing act. We use vias anyway, but in a different way. Wrapping the bus in a full metal sheath on the outer layer and riveting the edge of the ground plane to the inner layer ground is usually sufficient to meet EMI specifications involving short digital traces.
A ground pour without a ground via can become a conduit for crosstalk between traces on either side of the ground shape. Removing the copper leaving an excess air gap is better than an unsupported metal icicle to serve as an antenna between two lines, whether they are the attacker (noisy) or the victim (noise sensitive).
Clocks are one of those things you can count on to be noisy. In terms of being a victim, the receive chain is probably the worst on the way to the input pin. It's not always obvious. Reset lines and other miscellaneous circuits can generate noise. Almost any type of sensor will fall victim, even if the aggressor is routed several layers below the sensing device. As far as circuits not related to the sensor are concerned, consider the entire board around the sensor to be no man's land. As always, please read the application note on the data sheet for layout.
We often classify and mark the metal layers on the PCB. The outer pair of layers are called the primary and secondary placement layers. The main placement layer can be on the top or bottom layer, depending on which has more components. It may also depend on the definition of the physical design team. If the busy side of the board is facing down in the cabinet, it may be marked as bottom, but it is considered the main side.
Regardless of the context, component placement layers can provide the best location for using copper overflow as a passive heat sink. Through-hole or surface mount pins can be attached directly to the shape. For better solderability, gaps and spokes that connect pins or pads to the outer ground plane define the shape.
Almost every component on a PCB generates heat as it does its job. The hottest location in the system happens to be where the chip is attached to the substrate or interposer. The junction temperature at this point determines the lifetime of the components and thus the lifetime of the system. A strong layout provides a hot path to success.
After the electromagnetic radiation is shielded, the radiation of the system will be reduced. This effectively reduces power consumption. All your good impedance practices help improve the efficiency of your power domain. When there are fewer discontinuities, components don't have to work as hard. It's a small thing over time.
Uncontrolled thermal excursions can lead to early failure. Early failures can result in warranty work or a dime product replacement. Repairing or replacing a previously sold item reduces the profit from the initial sale. Lower profits lead to all sorts of bad situations and eventually bankruptcy. Don't close down busy with the plane.
One technique Qualcomm taught me is to cut the plane around the external oscillator with a gap that cuts the ground around the device and its resistance. The three sides that are not connected to the processor are framed by blanks. This will help limit the switching noise of the oscillator.
I always say put some ground vias near any socket. In that case, you'd provide an escape path on the next ground plane for all those oscillations to propagate their heartbeats onto some unsuspecting transmission line. So set back the ground vias a little on the quiet side of the gap. If there are no traces on layer 3, the gap may even be repeated on the first internal (layer 2) ground plane. If possible, rewire the wiring so that the noise is captured and absorbed back into the device.
When you're flooding a layer with a lot of routes, there are bound to be areas that get orphaned. The way traces are grouped will have a profound impact on the consequences of surface flooding. The first thing I would do is set a larger clearance rule between the copper overflow and the trace or shape.
The backoff will prevent the trace from becoming coplanar with unknown impedance. I use pullbacks of 0.50mm; about twice what is typical for an actual ground plane. If some buses are longer or have a higher data rate, they are 1mm long. It also helps to have a larger aperture so that the copper can't even get between two traces that are very close together.
Managing the "islands" of copper is setting a higher threshold for minimum size. A copper blob with only one ground via does no good. When it comes to power plane layers, there's also room to go down. Assuming you have a nice frame of ground vias around the board. Well, pull back the voltage plane and add a ground frame that connects the pin vias and completes the Faraday cage around the power plane. Your compliance team will see this, and you'll be treated like a saint. Handle with care, but don't be afraid of the ground.
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