1. The basic concept of vias
Via is one of the important components of multi-layer PCB, and the cost of drilling usually accounts for 30% to 40% of the cost of PCB fabrication. Simply put, every hole on a PCB can be called a via.
From the perspective of function, vias can be divided into two categories: one is used for electrical connection between layers; the other is used for device fixation or positioning.
In terms of process, these vias are generally divided into three categories, namely blind vias, buried vias and through vias.
Blind holes are located on the top and bottom surfaces of the printed circuit board, with a certain depth, for the connection of the surface circuit and the underlying inner circuit, and the depth of the hole usually does not exceed a certain ratio (diameter).
Buried vias refer to connection holes located in the inner layer of the printed circuit board, which do not extend to the surface of the circuit board.
The above two types of holes are located in the inner layer of the circuit board, and are completed by the through hole forming process before lamination. During the formation of the via hole, several inner layers may be overlapped.
The third type is called through-hole, which penetrates the entire circuit board and can be used for internal interconnection or as a mounting location hole for components. Because the through hole is easier to realize in the process and the cost is lower, most of the printed circuit boards use it instead of the other two kinds of through holes. The via holes mentioned below are considered as through holes unless otherwise specified.
From a design point of view, a via is mainly composed of two parts, one is the drill hole in the middle, and the other is the pad area around the drill hole.
The size of these two parts determines the size of the via. Obviously, when designing high-speed and high-density PCBs, designers always want the vias to be as small as possible, so that more wiring space can be left on the board. In addition, the smaller the vias, the smaller the parasitic capacitance. The smaller it is, the more suitable it is for high-speed circuits.
However, the reduction in hole size also brings an increase in cost, and the size of the via hole cannot be reduced indefinitely. It is limited by process technologies such as drilling and plating: the smaller the hole, the more drilling The longer the hole takes, the easier it is to deviate from the center; and when the depth of the hole exceeds 6 times the diameter of the drilled hole, it is not guaranteed that the hole wall will be uniformly plated with copper.
For example, if the thickness of a normal 6-layer PCB board (through hole depth) is 50Mil, then under normal conditions, the minimum drilling diameter that the PCB manufacturer can provide can only reach 8Mil. With the development of laser drilling technology, the size of the drill hole can also become smaller and smaller. Generally, the via hole with a diameter of less than or equal to 6Mils is called a micro hole.
Microvias are often used in HDI (High Density Interconnection) designs. Microvia technology allows vias to be directly punched on the pad (Via-in-pad), which greatly improves circuit performance and saves wiring space.
Vias appear as discontinuous discontinuities in impedance on the transmission line, causing signal reflection.
Generally, the equivalent impedance of the via is about 12% lower than that of the transmission line. For example, the impedance of a 50-ohm transmission line will be reduced by 6 ohms when passing through the via (specifically, it is related to the size of the via and the thickness of the board, not an absolute reduction).
However, the reflection caused by the discontinuous impedance of the via is actually very small. The reflection coefficient is only: (44-50)/(44+50)=0.06. The problems caused by the via are more concentrated in the parasitic capacitance and inductance. Impact.
2. Parasitic capacitance and inductance of vias
The via itself has parasitic stray capacitance. If it is known that the diameter of the solder resist area of the via on the ground layer is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate is is ε, the parasitic capacitance of the via is approximately: C=1.41εTD1/(D2-D1)
The main effect of the parasitic capacitance of the via on the circuit is to prolong the rise time of the signal and reduce the speed of the circuit.
For example, for a PCB board with a thickness of 50Mil, if the diameter of the via pad used is 20Mil (the diameter of the drill hole is 10Mils) and the diameter of the solder mask is 40Mil, we can use the above formula to approximately calculate the diameter of the via hole. The parasitic capacitance is roughly: C=1.41x4.4x0.050x0.020/(0.040-0.020)=0.31pF The rise time change caused by this part of the capacitance is roughly: T10-90=2.2C(Z0/2)=2.2x0 .31x(50/2)=17.05ps
It can be seen from these values that although the effect of the rise delay caused by the parasitic capacitance of a single via is not very obvious, if the via is used multiple times in the trace to switch between layers, multiple vias will be used. , careful consideration should be given to the design.
In actual design, the parasitic capacitance can be reduced by increasing the distance between the via and the copper area (Anti-pad) or reducing the diameter of the pad.
Parasitic capacitance and parasitic inductance also exist in vias. In the design of high-speed digital circuits, the harm caused by parasitic inductance of vias is often greater than the influence of parasitic capacitance.
Its parasitic series inductance will weaken the contribution of the bypass capacitor and reduce the filtering effect of the entire power system. We can simply calculate the approximate parasitic inductance of a via with the following empirical formula: L=5.08h[ln(4h/d)+1] where L is the inductance of the via, h is the length of the via, and d is The diameter of the center drilled hole.
It can be seen from the formula that the diameter of the via hole has little effect on the inductance, while the length of the via hole has the greatest influence on the inductance. Still using the above example, the inductance of the via can be calculated as: L=5.08x0.050[ln(4x0.050/0.010)+1]=1.015nH If the rise time of the signal is 1ns, then its equivalent impedance It is: XL=πL/T10-90=3.19Ω.
Such impedance can no longer be ignored when high-frequency current passes through. It should be noted that the bypass capacitor needs to pass through two vias when connecting the power supply layer and the ground layer, so that the parasitic inductance of the vias will be multiplied.
3. How to use vias
Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the adverse effects caused by the parasitic effects of vias, you can try to do as much as possible in the design:
3.1. From the perspective of cost and signal quality, select a via size of a reasonable size. If necessary, consider using vias of different sizes. For example, for power or ground vias, you can consider using larger sizes to reduce impedance, and for signal traces, you can use smaller vias. Of course, as the via size decreases, the corresponding cost also increases.
3.2. From the two formulas discussed above, it can be concluded that using a thinner PCB board is beneficial to reduce the two parasitic parameters of the via.
3.3. Try not to change the layers of the signal traces on the PCB, that is to say, try not to use unnecessary vias.
3.4. The power and ground pins should be drilled with vias nearby, and the shorter the leads between the vias and pins, the better. Consider making multiple vias in parallel to reduce the equivalent inductance.
3.5. Place some grounded vias near the vias where the signal changes layers to provide the closest return path for the signal. It is even possible to place some redundant ground vias on the PCB.
3.6. For high-density high-speed PCB boards, micro-vias can be considered.
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