How to Solve EMI Problems in Multilayer Circuit Board Design

There are many ways to solve the EMI problem. Modern EMI suppression methods include: the use of EMI suppression coatings, the selection of appropriate EMI suppression spare parts and EMI simulation design. This article starts from the basic circuit board layout. The editor of the panel technology manufacturer will discuss with you the role and design skills of layered stacking of PCB multilayer circuit boards in controlling EMI radiation.

Reasonable placement of capacitors with appropriate capacity near the power pins of the IC can make the IC output voltage jump faster. However, the problem does not end there. Due to the finite frequency response of capacitors, this prevents them from generating the harmonic power needed to cleanly drive the IC's output over the full frequency band. In addition, the transient voltages developed on the power busbars will create a voltage drop across the inductance of the decoupling path, and these transient voltages are the main source of common-mode EMI interference. How should we solve these problems?

In the case of an IC on our board, the power plane around the IC can be thought of as a good high-frequency capacitor that harvests the energy leaked by the discrete capacitors that provide high-frequency energy for a clean output. In addition, the inductance of a good power supply layer should be small, so that the transient signal synthesized by the inductance is also small, thereby reducing common mode EMI.

Of course, the wiring from the power plane to the IC power pins must be as short as possible, because the rising edge of the digital signal is getting faster and faster, and it is best to connect directly to the pad where the IC power pins are located, which is discussed separately.

To control common-mode EMI, the power plane must be a reasonably well-designed pair of power planes to facilitate decoupling and have sufficiently low inductance. How good is good, one might ask? The answer depends on the layering of the power supply, the materials between the layers, and the operating frequency (that is, a function of the IC's rise time). Usually, the spacing of the power layer is 6mil, and the interlayer is FR4 glass fiber board material, and the equivalent capacitance of the power layer per square inch is about 75pF. Obviously, the smaller the layer spacing, the greater the capacitance.

There are not many devices with rise times of 100 to 300ps, but at the current rate of development of ICs, there will be a high proportion of devices with rise times in the range of 100 to 300ps. For circuits with rise times of 100 to 300ps, 3mil layer spacing will no longer be suitable for most applications. At that time, it was necessary to use layering techniques with a layer spacing of less than 1 mil and replace the FR4 fiberglass board dielectric material with a material with a very high dielectric constant. Now, ceramics and ceramics can meet the design requirements of 100 to 300ps rise time circuits.

Although new materials and methods may be adopted in the future, for common today 1 to 3ns rise time circuits, 3 to 6mil interlayer spacing, and FR4 dielectric materials, it is usually sufficient to handle high-end harmonics and to keep transients low enough, that is to say , common mode EMI can be reduced very low. The PCB layered stackup design examples given in this article will assume a layer spacing of 3 to 6 mils.

From the signal routing point of view, a good layering strategy should be to place all signal traces on one or several layers next to power or ground planes. For power, a good layering strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer is as small as possible, which is what we call the "layering" strategy.

What stacking strategies help shield and suppress EMI? The following layered stacking scheme assumes that the supply current flows on a single layer, and that a single voltage or multiple voltages are distributed on different parts of the same layer. The case of multiple power planes is discussed later.

There are several potential issues with four-layer board designs. First of all, for a traditional four-layer board with a thickness of 62 mil, even if the signal layer is on the outer layer and the power and ground layers are on the inner layer, the distance between the power layer and the ground layer is still too large.

If cost requirements are a priority, consider the following two alternatives to traditional four-layer boards. Both solutions can improve EMI suppression performance, but only when the component density on the board is low enough and there is enough area around the components (where the required power supply copper layer is placed).

The first one is the preferred solution. The outer layers of the PCB are the ground layers, and the two middle layers are the signal/power layers. The power supply on the signal layer is routed with wide traces, which makes the path impedance of the power supply current low, and the impedance of the signal microstrip path is also low. From an EMI control standpoint, this is the best four-layer PCB structure available. In the second scheme, the outer layer takes the power and ground, and the middle two layers take the signal. Compared with the traditional four-layer board, the improvement of this scheme is smaller, and the interlayer impedance is as poor as the traditional four-layer board.

If trace impedance is to be controlled, the above stacking schemes require very careful routing of traces under the power and ground copper islands. In addition, copper islands on power or ground planes should be interconnected as closely as possible to ensure DC and low frequency connectivity.

If the component density on the four-layer circuit board is relatively high, it is better to use a six-layer board. However, some stacking schemes in the design of the six-layer circuit board are not good enough to shield the electromagnetic field, and have little effect on reducing the transient signal of the power busbar. Two examples are discussed below.

In the first example, the power and ground are placed on the 2nd and 5th layers respectively. Due to the high impedance of the power supply copper coating, it is very unfavorable to control the common mode EMI radiation. However, from the point of view of impedance control of the signal, this method is quite correct.

The second example places power and ground on the 3rd and 4th layers, respectively. This design solves the problem of power supply copper cladding impedance. Due to the poor electromagnetic shielding performance of the 1st and 6th layers, the differential mode EMI increases. If the number of signal traces on the two outer layers is minimal and the trace length is short (less than 1/20 of the wavelength of the highest harmonic of the signal), this design can solve the differential mode EMI problem. The suppression of differential mode EMI is particularly good by filling the non-component and non-trace areas on the outer layer with copper and grounding the copper-clad area (every 1/20 wavelength is an interval). As mentioned earlier, the copper area should be connected to the internal ground plane at multiple points.

The general high-performance six-layer board design generally uses the 1st and 6th layers as ground layers, and the 3rd and 4th layers for power and ground. EMI suppression is excellent due to two centered dual microstrip signal line layers between the power and ground planes. The disadvantage of this design is that there are only two layers of traces. As mentioned earlier, the same stackup can be achieved with a traditional 6-layer board if the outer layer traces are short and copper is placed in the no-trace area.

Another six-layer board layout is Signal, Ground, Signal, Power, Ground, Signal, which enables the environment required for advanced signal integrity designs. The signal layer is adjacent to the ground plane, and the power and ground planes are paired. Obviously, the downside is the unbalanced stacking of layers.

This usually causes trouble in manufacturing. The solution to the problem is to fill all the blank areas of the third layer with copper. After copper filling, if the copper density of the third layer is close to the power layer or the ground layer, this multilayer circuit board can be loosely counted as a structural balance. circuit board. The copper filling area must be connected to power or ground. The distance between the connecting vias is still 1/20 wavelength, not necessarily everywhere, but ideally should be connected.