As a hardware /PCB/SI engineer, a basic daily operation, from plate selection, PP selection, copper foil selection, and then the allocation of thickness, I believe experienced fans of the design of the lamination have got seven, eight, eight. But have you thought about this difference in design?
The conventional stacking operation method we have understood, is nothing more than to see the length of the meal. The length determines the level of the plate we want, and then PP tries to choose the best, that is, try not to choose a single sheet 106 or 1080 (don't ask why, we will be angry). Then choose the thickness of PP/core and calculate the line width/line distance of the corresponding impedance, and give it to the board factory to confirm it is basically OK.
But there's a very important point that I don't know if you've noticed when you're designing layering, or when you're looking at other people's layering. All right, let's give you an example.
Suppose that when we make a laminated design of a very thick backplane, a combination of ground - signal layer - ground can be divided into 15mil by distributing the number of line layers, as shown in the following figure:
After opening the line-up of your PP and CORE, the question arises, how do you choose to allocate PP/core in the upper and lower layers?
According to the above parameters, there are many combinations, such as 3milPP-12mil Core, or 5milPP-10mil Core, so let's choose the two most extreme combinations, as follows:
Is there any difference between these two layers? Isn't it that different PP and CORE are used to make up enough thickness? If you calculate the impedance, you'll see the biggest difference.
We have roughly figured out the time relationship for you, and the line width and line distance between the two layers are like this:
Speaking of the line width difference, you will know the biggest secret about it, that is, what? You say it out loud!
Yeah, that's wear and tear. If it is the same 10inch cable, the loss of 4mil line width and 6mil line width can be much different at 10GHz.
In the case of a long line or a tight margin, this invisible difference is very important. Think about it, if the line goes to 20inch, and then the speed is 25Gbps, the gap is even greater.
In our style, this is basically the end of the story. However, there will be a reversal of this plot, originally wanted to be left to answer the question and then analyzed, but fans may know our consistent routine, answer is to answer the question of netizens, and not so classic as the text on Monday, so simply put the reversal of the plot in advance to reveal the plot.
Have you ever thought that 6mil will be wider than 4mil line width (this is not fei words?) . We know that the space of the board is certain, if a pair of difference lines occupy more than 2W+S, then the distance between the difference pair and the difference pair is close, we ensure that the center distance between the two cases is the same premise of simulation, of course, we want to see the crosstalk results in two cases.
The plot is reversed, 6mil line width is bad on crosstalk. Of course, it is normal to think about it, the line width is wide, the space is used here, then the spacing between the pair is naturally close, because the space is determined, depending on whether you use the line width or the spacing there.
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