The standard package used to house a variety of advanced multifunctional semiconductor devices, such as FPgas and microprocessors, is the ball gate Array (BGA). Components in BGA packages are used in a wide range of embedded designs, both as host processors and as peripheral devices such as memory. BGA has changed significantly over the years to keep up with technological advances by chip manufacturers, and variants of the BGA package are used in dedicated leadless packages for a variety of devices. However, in HDI design and layout wiring, the most difficult element to deal with is the BGA with a high pin number and small pin spacing.
BGA packages can be divided into standard BGA and micro BGA. In today's electronics, the need for I/O availability presents many challenges, even for experienced PCB designers, especially when it comes to multilayer wiring. What strategies can we employ to successfully overcome these BGA PCB design challenges?
Start PCB layout with BGA
Since BGA is usually the main processor in the device, and they may need to be connected to many other components on the board, it is common practice to place the largest BGA component first and use it to start layout planning the PCB layout. While you don't have to place this component first or lock its position after it is placed, the maximum BGA will partially determine the number of layers as well as the fan-out strategy in your component wiring.
When starting PCB layout wiring with BGA, there are a few tasks that need to be completed to ensure successful wiring:
1. Number of signal layers: Determining the number of signal layers required in the stack will affect the number of flat layers, as well as the width of the final wiring required to the design.
2. Fan out: How will the signal enter and exit the BGA? Is controlled impedance required? These issues will determine the number of layers in the stack, and then determine how the wires are routed inside each layer.
There are also issues of design performance and qualification levels. High reliability designs with BGA require product specific reliability standards of class 3/3A or higher. For example, some military aviation specifications will require pad sizes that exceed IPC-6012 Level 3 ring hole requirements. As a result, the standard dog bone fan-out may no longer be effective due to tolerances, ring holes, and solder shield requirements.
Having considered some of these points early in the design process, the PCB layout for BGA can now be addressed through three tasks.
BGA Strategy 1: Define a suitable outlet
The main challenge in BGA layout and wiring is to identify suitable exits that can be reliably manufactured and do not result in PCB rework after assembly. For BGA with a higher number of layers, outlet planning involves a path through multiple rows of pins. Some of these tracks may carry high-speed signals and need to be properly spaced to prevent crosstalk. Other signals may be slower configured signals that can be packed more closely together, reducing the risk of crosstalk or too much noise.
The following example shows BGA circuitous wiring on two inner layers. Here we can see that on these inner layers, the wiring is routed to multiple lines through the holes (more than two lines), which is appropriate considering we are not wiring to the surface pins. On the surface, due to the size of the pads in the BGA connection plate pattern, the need for clearance, and the type of fan out (especially the dog bone fan out), the most common practice is to wire only to the outer two rows.
On the top layer below the BGA, many of the pads in the pad pattern need to be connected to the through holes in order to connect to the inner layer of the entire PCB. For widely spaced BGA (up to 1 mm), dog bone fanout is the standard method for making these connections. These small tracks connected to the through-hole can enter the outer two rows of pins of the surface layer (below the BGA) and enter the remaining inner pad through the through-hole of the inner layer.
Although the dog bone fan-out is the standard method for large-pitch BGA, pan through holes give you more flexibility in the surface layer. As the pin spacing becomes smaller, so does the width of the line required to reach the BGA between the pins of each layer. For controlled impedance signals, this means you will need thinner laminates and ultimately HDI technology to ensure you can wire to BGA. The fan-out type will eventually change from dog bone type to pan pass type.
BGA Strategy 2: Grounding and power
In a large BGA, it is likely that there will be multiple pins dedicated to ground and power. In some components, especially large processors that must support multiple high-speed digital interfaces, most of the pins may be dedicated to power and ground. In addition, the component may require multiple voltage levels, which means that power from multiple sources needs to be routed to the board. The easiest way to manage a BGA power connection is to use a power rail, which is usually located on one or two flat layers. Placing the power supply and ground on adjacent layers with thin dielectric isolation layers also helps to maintain power integrity by providing high level inter-capacitance.
Although we always talk about outgoing or roundabout wiring below the BGA, this is not the only type of wiring you will create near the BGA pins. Power rails, connections to ground plane layers or polygons, and wiring between pins may all need to be performed under the same BGA. This means that in addition to the power/ground polygon on the same layer, you may also see wiring between pins.
BGA Strategy 3: Determine PCB layer stacking
The BGA pin arrangement and the I/O count on the BGA can be used to determine the number of layers required in the PCB stack. Once the designer determines the line width required to route the controlled impedance line into the BGA, the layer thickness required to maintain the impedance can be determined. Adding the number of rows in the BGA, you can now calculate the total number of signal layers required in the PCB stack.
Normally, the outer first two rows of the BGA device do not require holes, so it can be routed in the surface layer. This is the case with dog bone fan-outs, pan holes or alternative fan-outs. This pattern can then be repeated throughout the BGA to determine the total number of layers needed to fan out the signal. GND pins are usually interlaced between signal pins, and GND should be interlaced between signal layers to provide isolation when needed. The following figure shows how the number of rows is counted in BGA to determine the number of signal layers required.
In the example below, we show an inverted BGA chip where some of the pins have been removed from the inner row. Because some of these balls have been removed, signals can be routed there and reach these inner pins, so more than 2 rows can be accessed from the inner layer. The main internal blocks on this particular BGA may be used for power and grounding, and at least two layers are required. With these layers and back layers, the total number of layers required to completely fan out and wire this BGA will be at least 6 layers.
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